1. Field of the Invention
The present invention generally relates to a frequency detector for a timing recovery system. More particularly, the present invention relates to a frequency detector that adjusts the parameters of a timing recovery system based on the frequency of the incoming timing jitter, which optimizes the timing recovery system for both low frequency and high frequency timing jitter.
2. Discussion of the Related Art
Networking applications have become very popular in recent years, particularly in response to an explosion in the use and variety of networks employed in a vast array of computing environments. Accordingly, many advances have been made in the related technology in order to improve the quality of these networking systems. For example, fully integrated transceivers for T1 network channel service units (CSUs) and integrated services digital network (ISDN) primary rate interface applications are known in the art and are presently commercially available. These devices, such as the Intel LXT360 T1/E1 transceiver, are useful for networking applications, such as timing recovery in T1 network systems. However, there are obstacles that prevent such systems from providing better jitter tolerancexe2x80x94a desirable quality in communications networks and other networking applications. Such obstacles may include exceptionally large amplitude jitter, a wide variation in data density, large amounts of cable attenuation, and imperfect equalization.
Jitter is the general term used to describe the noise or uncertainty in the period of incoming data in a communications system. In an ideal system, bits arrive at time increments that are integer multiples of a bit repetition time. However, in a real-world system, data pulses arrive at times that deviate from these integer multiples. This deviation may cause errors in the transmission of data, particularly when the data is transmitted at high speeds. The deviation or variation may be in the amplitude, frequency, or phase of the data. Jitter may occur due to a number of causes, including inter-symbol interference, frequency differences between the transmitter and receiver clock, noise, and the non-ideal behavior of the receiver and transmitter clock generation circuits.
Jitter is a problem of particular import in digital communications systems. First, jitter causes the received signal to be sampled at a non-optimal sampling point. This occurrence reduces the signal-to-noise ratio at the receiver and thus limits the information rate. Second, in conventional systems, each receiver typically extracts its receive sampling clock from the incoming data signal. Jitter makes this task significantly more difficult. Third, in long-distance transmission systems, where multiple repeaters reside in a chain, jitter accumulates. That is, each receiver extracts a clock from the incoming bit stream, re-times the data, and re-transmits the data utilizing the recovered clock. Each subsequent receiver thus sees a progressively larger degree of input jitter.
Although current systems provide for jitter attenuation, these systems are not robust enough to handle wide variations between high-frequency jitter and low-frequency jitter. Moreover, current systems are not sensitive and stable enough to detect minor variations of high-frequency jitter and low-frequency jitter and may cause these systems to stall. In certain applications, such as T1 networks, where the incoming timing jitter could be quite large and could be over a wide frequency range, it is difficult to design, for example, a phase locked loop (PLL) that can simultaneously track large-amplitude low-frequency jitter and provide enough rejection of high frequency jitter.
Accordingly, there is a need for a timing recovery system having a frequency detector that tolerates large amplitude jitter with a wide frequency range, as well as having accurate and robust jitter detection.